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ltc1647-1/ltc1647-2/ltc1647-3 1 , ltc and lt are registered trademarks of linear technology corporation. dual hot swap controllers the ltc ? 1647-1/ltc1647-2/ltc1647-3 are dual hot swap tm controllers that permit a board to be safely in- serted and removed from a live backplane. using external n-channel mosfets, the board supply voltages can be ramped up at a programmable rate. a high side switch driver controls the mosfet gates for supply voltages ranging from 2.7v to 16.5v. a programmable electronic circuit breaker protects against overloads and shorts. the on pins are used to control board power or clear a fault. the ltc1647-1 is a dual hot swap controller with a common v cc pin, separate on pins and is available in an so-8 package. the ltc1647-2 is similar to the ltc1647-1 but combines a fault status flag with automatic retry at the on pins and is also available in the so-8 package. the ltc1647-3 has individual v cc pins, on pins and fault status pins for each channel and is available in a 16-lead narrow ssop package. n hot board insertion n electronic circuit breaker n portable computer device bays n hot plug disk drive n allows safe board insertion and removal from a live backplane n programmable electronic circuit breaker n fault output indication n programmable supply voltage power-up rate n high side drive for external mosfet switches n controls supply voltages from 2.7v to 16.5v n undervoltage lockout v id controller for two device bays hot swap is a trademark of linear technology corporation. v cc sense 1 1 86 on1 c3 4.7nf 2 on2 on1 3.3v v id supply on2 3 gnd 4 gate 1 sense 2 75 gate 2 ltc1647-1 connector #1 1394 phy and/or usb port device #1 c1 4.7nf r2 10 r1 0.1 q1 1/2 mmdf3n02hd r5 0.1 q2 1/2 mmdf3n02hd r3** r4** c load * *c load is user-selected based on the device requirements ** r3, r4, r7 and r8 are optional discharge resistors when devices are powered-off q1, q2: on semiconductor r6 10 + connector #2 1394 phy and/or usb port device #2 1647-1/2/3 ta01 r7** r8** c load * + 5ms/div 2.5v/div 1647-1/2/3 ta01a v on v gate v out on/off sequence applicatio s u features typical applicatio u descriptio u
ltc1647-1/ltc1647-2/ltc1647-3 2 supply voltage (v cc ) ............................................... 17v input voltage (sense) ................. C 0.3v to (v cc + 0.3v) input voltage (on) .....................................C 0.3v to 17v output voltage (fault) .............................C 0.3v to 17v output voltage (gate) ......... internally limited (note 3) absolute axi u rati gs w ww u package/order i for atio uu w (note 1) electrical characteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. v cc = 5v unless otherwise noted. (note 2) operating temperature range commercial ............................................. 0 c to 70 c industrial ............................................ C 40 c to 85 c storage temperature range ................. C 65 c to 150 c lead temperature (soldering, 10 sec).................. 300 c order part number s8 part marking t jmax = 150 c, q ja = 130 c/w consult factory for military grade parts. 16471 16471i ltc1647-1cs8 ltc1647-1is8 t jmax = 150 c, q ja = 130 c/w t jmax = 150 c, q ja = 130 c/w order part number s8 part marking 16472 16472i ltc1647-2cs8 ltc1647-2is8 order part number gn part marking 16473 16473i LTC1647-3CGN ltc1647-3ign symbol parameter conditions min typ max units v cc v ccx supply range operating range l 2.7 16.5 v i cc v cc supply current (note 4) on1, on2 = v cc1 = v cc2 , i cc = i cc1 + i cc2 l 1.0 6 ma i ccx v ccx supply current (note 5, ltc1647-3) onx = v ccx , i ccx individually measured, l 0.5 5 ma v cc1 = 5v, v cc2 = 12v or v cc1 = 12v, v cc2 = 5v v lko v ccx undervoltage lockout coming out of uvlo (rising v ccx ) l 2.30 2.45 2.60 v v lkh v ccx undervoltage lockout hysteresis 210 mv v cb circuit breaker trip voltage v cb = v ccx C v sensex l 40 50 60 mv i cp gate x output current onx high, fault x high, v gate = gnd (sourcing) l 61014 m a onx low, fault x high, v gate = v cc (sinking) 50 m a onx high, fault x low, v gate = 15v (sinking) 50 ma 1 2 3 4 8 7 6 5 top view sense 1 sense 2 gate 1 gate 2 v cc on1 on2 gnd s8 package 8-lead plastic so 1 2 3 4 8 7 6 5 top view sense 1 sense 2 gate 1 gate 2 v cc on1/fault 1 on2/fault 2 gnd s8 package 8-lead plastic so 1 2 3 4 5 6 7 8 top view gn package 16-lead plastic ssop 16 15 14 13 12 11 10 9 v cc1 on1 fault 1 on2 fault 2 nc nc gnd v cc2 sense 1 sense 2 gate 1 gate 2 nc nc nc
ltc1647-1/ltc1647-2/ltc1647-3 3 d v gate external mosfet gate drive (v gate C v cc ), v cc1 = v cc2 = 5v l 10 13 17 v (v gate C v cc ), v cc1 = v cc2 = 12v l 10 15 19 v v onhi onx threshold high l 1.20 1.29 1.38 v v onlo onx threshold low l 1.17 1.21 1.25 v v onhyst onx hysteresis 70 mv i in onx input current on = gnd or v cc l 1 10 m a v ol fault x output low voltage i o = 1ma, v cc = 5v l 0.4 v (ltc1647-2, ltc1647-3) i o = 5ma, v cc = 5v 0.8 v i leak fault x output leakage current no fault, fault x = v cc = 5v 1 10 m a (ltc1647-3) t fault circuit breaker delay time v ccx C v sensex = 0 to 100mv 0.3 m s t reset circuit breaker reset time onx high to low, to fault x high l 50 100 m s t on turn-on time onx low to high, to gate x on 2 m s t off turn-off time onx high to low, to gate x off 1 m s electrical characteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. v cc = 5v unless otherwise noted. (note 2) symbol parameter conditions min typ max units note 1: absolute maximum ratings are those values beyond which the life of a device may be impaired. note 2: all currents into device pins are positive; all currents out of device pins are negative. all voltages are referenced to ground unless otherwise specified. note 3: an internal zener on the gate pins clamp the charge pump voltage to a typical maximum operating voltage of 28v. external overdrive of the gate pin beyond the internal zener voltage may damage the device. the gate capacitance must be < 0.15 m f at maximum v cc . if a lower gate pin clamp voltage is desired, use an external zener diode. note 4: the total supply current i cc is measured with v cc1 and v cc2 connected internally (ltc1647-1, ltc1647-2) or externally (ltc1647-3). note 5: the individual supply current i ccx is measured on the ltc1647-3. the lower of the two supplies, v cc1 and v cc2 , will have its channels current. the higher supply will carry the additional supply current of the charge pump and the bias generator beside its channels current. ltc1647-1 pinout pin description 1v cc 2 on1 3 on2 4 gnd ltc1647-3 pinout pin description 1v cc1 2 on1 3 fault 1 4 on2 5 fault 2 6nc 7nc 8 gnd pin description 5 gate 2 6 gate 1 7 sense 2 8 sense 1 pin description 9nc 10 nc 11 nc 12 gate 2 13 gate 1 14 sense 2 15 sense 1 16 v cc2 ltc1647-2 pinout pin description 1v cc 2 on1 and fault 1 (internally tied together) 3 on2 and fault 2 (internally tied together) 4 gnd pin description 5 gate 2 6 gate 1 7 sense 2 8 sense 1 ltc1647-1 does not have the fault status feature. the onx/fault x must be connected to a driver via a resistor if the autoretry feature is being used.. pi u tables
ltc1647-1/ltc1647-2/ltc1647-3 4 v cc (v) 2 6 10 14 18 4 8 12 16 i cc (ma) 1647-1/2/3 g01 6 5 4 3 2 1 0 t a = 25 c i cc = i cc1 + i cc2 v cc = v cc1 = v cc2 = on1 = on2 temperature ( c) 75 50 25 0 25 50 75 100 125 150 i cc (ma) 1647-1/2/3 g02 6 5 4 3 2 1 0 i cc = i cc1 + i cc2 v cc = v cc1 = v cc2 = on1 = on2 v cc = 15v v cc = 12v v cc = 3v v cc = 5v v cc2 (v) 02468101214161820 i cc1 (ma) 1647-1/2/3 g03 5 4 3 2 1 0 t a = 25 c v cc1 = 15v v cc1 = 12v v cc1 = 3v v cc1 = 5v v cc2 (v) 02468101214161820 i cc2 (ma) 1647-1/2/3 g04 5 4 3 2 1 0 t a = 25 c v cc1 = 15v v cc1 = 12v v cc1 = 3v v cc1 = 5v v cc (v) 02468101214161820 (v gate ?v cc ) (v) 1647-1/2/3 g05 20 18 16 14 12 10 8 6 4 2 0 t a = 25 c v cc = v cc1 = v cc2 v cc (v) 02468101214161820 v gate (v) 1647-1/2/3 g06 30 25 20 15 10 5 0 t a = 25 c v cc = v cc1 = v cc2 temperature ( c) (v gate ?v cc ) (v) 1647-1/2/3 g07 20 18 16 14 12 10 8 6 4 2 0 v cc = v cc1 = v cc2 75 50 25 0 25 50 75 100 125 150 v cc = 15v v cc = 12v v cc = 3v v cc = 5v temperature ( c) v gate (v) 1647-1/2/3 g08 35 30 25 20 15 10 5 0 v cc = v cc1 = v cc2 75 50 25 0 25 50 75 100 125 150 v cc = 15v v cc = 12v v cc = 3v v cc = 5v v cc2 (v) 02468101214161820 (v gate1 ?v cc1 ) (v) 1647-1/2/3 g09 20 18 16 14 12 10 8 6 4 2 0 v cc1 = 15v v cc1 = 12v v cc1 = 3v v cc1 = 5v t a = 25 c (ltc1647-3) i cc vs v cc i cc vs temperature i cc1 vs v cc2 i cc2 vs v cc2 (v gate C v cc ) vs v cc v gate vs v cc (v gate C v cc ) vs temperature v gate vs temperature (v gate1 C v cc1 ) vs temperature typical perfor a ce characteristics uw
ltc1647-1/ltc1647-2/ltc1647-3 5 v cc2 (v) 02468101214161820 v gate1 (v) 1647-1/2/3 g10 35 30 25 20 15 10 5 0 t a = 25 c (ltc1647-3) v cc1 = 15v v cc1 = 12v v cc1 = 3v v cc1 = 5v v cc (v) 02468101214161820 gate output source current ( a) 1647-1/2/3 g11 14 13 12 11 10 9 8 7 6 t a = 25 c v cc = v cc1 =v cc2 temperature ( c) gate output source current ( a) 1647-1/2/3 g12 14 13 12 11 10 9 8 7 6 v cc = v cc1 = v cc2 = 5v 75 50 25 0 25 50 75 100 125 150 v cc (v) 02468101214161820 gate output sink current ( a) 1647-1/2/3 g13 100 90 80 70 60 50 40 30 20 10 0 t a = 25 c temperature ( c) gate output sink current ( a) 1647-1/2/3 g14 55 54 53 52 51 50 49 48 47 46 45 v cc = 5v 75 50 25 0 25 50 75 100 125 150 v cc (v) 02468101214161820 gate fast pull-down current (ma) 1647-1/2/3 g15 60 55 50 45 40 35 30 t a = 25 c temperature ( c) gate fast pull-down current (ma) 1647-1/2/3 g16 80 70 60 50 40 30 20 10 0 75 50 25 0 25 50 75 100 125 150 v cc = v cc1 = v cc2 = 5v v cc (v) 02468101214161820 circuit breaker trip voltage (mv) 1647-1/2/3 g17 60 58 56 54 52 50 48 46 44 42 40 t a = 25 c temperature ( c) circuit breaker trip voltage (mv) 1647-1/2/3 g18 60 58 56 54 52 50 48 46 44 42 40 75 50 25 0 25 50 75 100 125 150 v cc = 15v v cc = 12v v cc = 5v v cc = 3v v gate1 vs v cc2 gate output source current vs v cc gate output source current vs temperature gate output sink current vs v cc gate output sink current vs temperature gate fast pull-down current vs v cc gate fast pull-down current vs temperature circuit breaker trip voltage vs v cc circuit breaker trip voltage vs temperature typical perfor a ce characteristics uw
ltc1647-1/ltc1647-2/ltc1647-3 6 undervoltage lockout threshold vs temperature on threshold voltage vs v cc on threshold voltage vs temperature fault v ol vs v cc fault v ol vs temperature t fault vs v cc t fault vs temperature circuit breaker reset time vs v cc circuit breaker reset time vs temperature typical perfor a ce characteristics uw temperature ( c) undervoltage lockout threshold (v) 1647-1/2/3 g19 2.6 2.5 2.4 2.3 2.2 2.1 75 50 25 0 25 50 75 100 125 150 rising edge falling edge v cc (v) 02468101214161820 on threshold voltage (v) 1647-1/2/3 g20 1.35 1.30 1.25 1.20 1.15 t a = 25 c high low temperature ( c) on threshold voltage (v) 1647-1/2/3 g21 1.35 1.30 1.25 1.20 1.15 75 50 25 0 25 50 75 100 125 150 v cc = 5v high low v cc (v) 02468101214161820 fault v ol (v) 1647-1/2/3 g22 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 t a = 25 c i ol = 5ma i ol = 1ma temperature ( c) fault v ol (v) 1647-1/2/3 g23 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 v cc = 5v i ol = 5ma i ol = 1ma 75 50 25 0 25 50 75 100 125 150 v cc (v) 02468101214161820 t fault ( s) 1647-1/2/3 g24 1.0 0.8 0.6 0.4 0.2 0 t a = 25 c temperature ( c) t fault ( s) 1647-1/2/3 g25 1.0 0.8 0.6 0.4 0.2 0 75 50 25 0 25 50 75 100 125 150 v cc = 15v v cc = 12v v cc = 3v v cc = 5v v cc (v) 02468101214161820 circuit breaker reset time ( s) 1647-1/2/3 g26 70 60 50 40 30 t a = 25 c temperature ( c) circuit breaker reset time ( s) 1647-1/2/3 g27 60 58 56 54 52 50 48 46 44 42 40 75 50 25 0 25 50 75 100 125 150 v cc = 3v v cc = 5v v cc = 12v v cc = 15v
ltc1647-1/ltc1647-2/ltc1647-3 7 v cc1 (ltc1647-3): channel 1 positive supply input. the supply range for normal operation is 2.7v to 16.5v. the supply current, i cc1 , is typically 1ma. channel 1s under- voltage lockout (uvlo) circuit disables gate 1 until the supply voltage at v cc1 is greater than v lko (typically 2.47v). gate 1 is held at ground potential until uvlo deactivates. if on1 is high and v cc1 is above the uvlo threshold voltage, gate 1 is pulled high by a 10 m a current source. if v cc1 falls below (v lko C v lkh ), gate 1 is pulled immediately to ground. the internal reference and the common charge pump are powered from the higher of the two v cc inputs, v cc1 or v cc2 . v cc2 (ltc1647-3): channel 2 positive supply input. see v cc1 for functional description. v cc : the common positive supply input for the ltc1647-1 and the ltc1647-2. v cc1 and v cc2 are internally con- nected together. gnd: chip ground. on1: channel 1 on input. the threshold at the on1 pin is set at 1.28v with 70mv hysteresis. if uvlo and the circuit breaker of channel 1 are inactive, a logic high at on1 enables the 10 m a charge pump current source, pulling the gate 1 pin above v cc1 . if the on1 pin is pulled low, the gate 1 pin is pulled to ground by a 50 m a current sink. on1 resets channel 1s electronic circuit breaker by pull- ing on1 low for greater than one t reset period (50 m s). a low-to-high transition at on1 restarts a normal gate 1 pull-up sequence. on2: channel 2 on input. see on1 for functional descrip- tion. fault 1: channel 1 open-drain fault status output. fault 1 pin pulls low after 0.3 m s (t fault ) if the circuit breaker measures greater than 50mv across the sense resistor connected between v cc1 and sense 1. if fault 1 pulls low, gate 1 also pulls low. fault 1 remains low until on1 is pulled low for at least one t reset period. fault 2: channel 2 open-drain fault status output. see fault 1 for functional description. sense 1: channel 1 circuit breaker current sense input. load current is monitored by a sense resistor connected between v cc1 and sense 1. the circuit breaker trips if the voltage across the sense resistor exceeds 50mv (v cb ). to disable the circuit breaker, connect sense 1 to v cc1 . in order to obtain optimum performance, use kelvin-sense connections between the v cc and sense pins to the current sense resistor. sense 2: channel 2 circuit breaker current sense input. see sense 1 for functional description. gate 1: channel 1 n-channel mosfet gate drive output. an internal charge pump guarantees at least 10v of gate drive from a 5v supply. two zener clamps are incorpo- rated at the gate 1 pin; one zener clamps gate 1 approximately 15v above v cc and the second zener clamps gate 1 appoximately 28v above gnd. the rise time at gate 1 is set by an external capacitor connected between gate 1 and gnd and an internal 10 m a current source provided by the charge pump. the fall time at gate 1 is set by the 50 m a current sink if on1 is pulled low. if the circuit breaker is tripped or the supply voltage hits the uvlo threshold, a 50ma current sink rapidly pulls gate 1 low. gate 2: channel 2 n-channel mosfet gate drive output. see gate 1 for functional description. nc: no connection. pi fu ctio s uuu
ltc1647-1/ltc1647-2/ltc1647-3 8 ltc1647-1 ltc1647-2 block diagra s w 3 + 50 s filter + 1.21v 50mv channel one channel two (duplicate of channel one) 10 a cp + 50 a 2.45v uvl charge pump reference 1.21v on2 1647-1/2/3 bd1 7 sense 2 5 gate 2 4 gnd 1 v cc cp 2 on1 8 sense 1 6 gate 1 3 + 50 s filter + 1.21v 50mv channel one channel two (duplicate of channel one) 10 a cp + 50 a fault 2.45v uvl charge pump reference 1.21v on2/fault 2 1647-1/2/3 bd2 7 sense 2 5 gate 2 4 gnd 1 v cc cp 2 on1/fault 1 8 sense 1 6 gate 1
ltc1647-1/ltc1647-2/ltc1647-3 9 v cc selection circuit the ltc1647-3 features separate supply inputs (v cc1 and v cc2 ) for each channel. the reference and charge pump circuit draw supply current from the higher of the two supplies. an internal v cc selection circuit detects and makes the power connection automatically. this allows a 3v channel to have standard mosfet gate overdrive when the other channel is 5v. an internal zener clamps gate about 15v above v cc . if both supplies are connected together (internally for ltc1647-1 and ltc1647-2 or externally for ltc1647-3), the reference and charge pump circuit draw equal current from both pins. electronic circuit breaker each channel of the ltc1647 features an electronic circuit breaker to protect against excessive load current and short-circuits. load current is monitored by sense resis- tor r1 as shown in figure 1. the circuit breaker threshold, v cb , is 50mv and it exhibits a response time, t fault , of approximately 300ns. if the voltage between v cc and sense exceeds v cb for more than t fault , the circuit breaker trips and immediately pulls gate low with a 50ma current sink. the mosfet turns off and fault pulls low. the circuit breaker is cleared by pulling the on pin low for a period of at least t reset (50 m s). a timing diagram of these events is shown in figure 2. the value of the sense resistor r1 is given by r1 = v cb /i trip ( w ) where v cb is the circuit breaker trip voltage (50mv) and i trip is the value of the load current at which the circuit breaker trips. kelvin-sense layout techniques between the sense resistor and the v cc and sense pins are highly recommended for proper operation. ltc1647-3 applicatio s i for atio wu u u block diagra s w 14 + 50 s filter + 1.21v 50mv channel one channel two (duplicate of channel one) 10 a cp + 50 a fault 2.45v uvl charge pump reference 1.21v sense 2 4 on2 5 fault 2 1647-1/2/3 bd3 16 v cc2 12 gate 2 8 gnd cp v cc selection 15 sense 1 13 gate 1 3 fault 1 2 on1 1 v cc1
ltc1647-1/ltc1647-2/ltc1647-3 10 the circuit breaker trip voltage has a tolerance of 20%; combined with a 5% sense resistor, the total tolerance is 25%. therefore, calculate r1 based on a trip current i trip of no less than 125% of the maximum operating current. do not neglect the effect of ripple current, which adds to the maximum dc component of the load current. ripple current may arise from any of several sources, but the worst offenders are switching supplies. a switching regulator on the load side will attempt to draw some ripple current from the backplane and this current passes through the sense resistor. similarly, output ripple from a switching regulator supplying the backplane will flow through the sense resistor and into the load capacitor. minimize the effects of ripple current by either filtering the v out line or adding an rc filter to the sense pin. a series inductance of 1 m h to 10 m h inserted between q1 and c load is adequate ripple current suppression in most cases. alternatively, a filter, consisting of r3 and c3(figure 3), simply filters the ripple component from the sense pin at the expense of response time. the added delay is given by t delay = C r3?c3?ln[1 C (v cb /r1 C i av )/(i pk C i av )] power mosfet selection power mosfets are classified into two catagories: stan- dard mosfets (r ds(on) specified at v gs = 10v) and logic- level mosfets (r ds(on) specified at v gs = 5v). the absolute maximum rating for v gs is typically 20v for standard mosfets. the maximum rating for logic-level mosfets is lower and ranges from 8v to 16v depending on the manufacturer and specific part number. some logic-level mosfets have a 20v maximum v gs rating. the ltc1647 is primarily targeted for standard mosfets; low supply voltage applications should use logic-level mosfets. gate overdrive as a function of v cc is illus- trated in the typical performance curves. if lower gate overdrive is desired, connect a diode in series with a zener between gate and v cc or between gate and v out as shown in figure 4. the r ds(on) of the external pass transistor must be low to make v ds a small percentage of v cc . at v cc = 3.3v, v ds + v cb = 0.1v yields 3% error at maximum load current. this restricts the choice of mosfets to very low r ds(on) . at higher v cc voltages, the r ds(on) requirement can be relaxed. mosfet package dissipation (p d and t j ) may restrict the value of r ds(on) . figure 1. supply control circuitry figure 2. current fault timing figure 3. filtering current ripple/glitches figure 4. optional gate clamp applicatio s i for atio wu u u sense 15 13 on1 2 fault on v cc v out fault 3 gnd 8 gate ltc1647-3 c1 10nf 1647-1/2/3 f01 r2 10 r1 0.01 q1 irf7413 c load + v cc 1 r3 10k t fault t reset v on v cc ? v sense v gate v fault 1647-1/2/3 f02 sense v cc v out gate ltc1647 c1 10nf c3 10nf 1647-1/2/3 f03 r2 10 r1 0.01 q1 irf7413 c load i pk = 7.5a i av = 2.5a i trip = v cb /r1 = 5a t delay = 10 s + v cc r3 1.5k v cc v out *user selected voltage clamp 1n4688 (5v) 1n4692 (7v): logic-level mosfet 1n4695 (9v) 1n4702 (15v): standard-level mosfet 1647-1/2/3 f04 r1 d1* d2 1n4148 d4* d2 1n4148 q1
ltc1647-1/ltc1647-2/ltc1647-3 11 power supply ramping v out is controlled by placing mosfet q1 in the power path (figure 1). r1 provides load current fault detection and r2 prevents mosfet high frequency oscillation. by ramping the gate of the pass transistor at a controlled rate (dv/dt = 10 m a/c1), the transient surge current (i = c load ?dv/dt = 10 m a?c load /c1) drawn from the main backplane is limited to a safe value when the board is inserted into the connector. when power is first applied to v cc , the gate pin pulls low. a low-to-high transition at the on pin initiates gate ramp- up. the rising dv/dt of gate is set by 10 m a/c1 (figure 5), where c1 is the total external capacitance between gate and gnd. the ramp-up time for v out is equal to t = (v cc ?c1)/10 m a. a high-to-low transition at the on pin initiates a gate ramp-down at a slope of C 50 m a/c1. this rate is usually adequate as the supply bypass capacitors take time to discharge through the load. if the on pin is connected to v cc , or is pulled high before v cc is first applied, gate is held low until v cc rises above the undervoltage lockout threshold, v lko (figure 6). once the threshold is exceeded, gate ramps at a controlled rate of 10 m a/c1. when the power supply is disconnected, the body diode of q1 holds v cc about 700mv below v out . the gate voltage droops at a rate determined by v cc . if v cc drops below v lko C v lkh , the ltc1647 enters uvlo and gate pulls down to gnd. autoretry the ltc1647-2 and ltc1647-3 are designed to allow an automatic reset of the electronic circuit breaker after a fault condition occurs. this is accomplished by pulling the on/fault (ltc1647-2) pin or the on and fault pins tied together (ltc1647-3) high through a resistor, r3, as shown in figure 7. an autoretry sequence begins if a fault occurs. if the circuit breaker trips, fault pulls the on pin low. after a t reset interval elapses, fault resets and r3 figure 5. supply turn-on/off with on figure 7. autoretry sequence applicatio s i for atio wu u u v cc + ? v gate v cc v cc v on c load discharges ramp-down slope = 50 a/c1 ramp-up slope = 10 a/c1 v out v gate 0v 0v 1647-1/2/3 f05 v cc + ? v gate v cc v cc v cc v lko v lko ? v lkh c load discharges v cc unplugged out of uvlo into uvlo fast ramp-down at undervoltage lockout v gate droop due to v cc ramp-up slope = 10 a/c1 v out v gate 0v 0v 1647-1/2/3 f06 sense 86 on/fault v cc v out fault on (5v logic) 2 gnd 4 gate ltc1647-2 c1 10nf r2 10 r1 0.01 q1 irf7413 c load + v cc 1 r3 15k c3 0.1 f t reset t delay t ramp v cc ?v sense v gate v fault 1647-1/2/3 f07
ltc1647-1/ltc1647-2/ltc1647-3 12 pulls the on pin up. c3 delays gate turn-on until the voltage at the on pin exceeds v ih . the delay time is t delay = Cr3?c3?ln[1C(v ih C v ol )/(v on C v ol )] gate ramps up at 10 m a/c1 until q1 conducts. if v out is still shorted to gnd, the cycle repeats. the ramp interval is about t ramp = v th ?c1/10 m a where v th is the threshold voltage of the external mosfet. hot circuit insertion when circuit boards are inserted into a live backplane or a device bay, the supply bypass capacitors on the board can draw huge transient currents from the backplane or the device bay power bus as they charge up. the transient currents can damage the connector pins and glitch the system supply, causing other boards in the system to reset or malfunction. the ltc1647 is designed to turn two positive supplies on and off in a controlled manner, allowing boards to be safely inserted or removed from a live backplane or device bay. the ltc1647 can be located before or after the connector as shown in figure 8. a staggered pcb connector can sequence pin conections when plugging and unplugging circuit boards. alternatively, the control signal can be generated by processor control. ringing good engineering practice calls for bypassing the supply rail of any circuit. bypass capacitors are often placed at the supply connection of every active device, in addition to one or more large value bulk bypass capacitors per supply rail. if power is connected abruptly, the bypass capacitors slow the rate of rise of voltage and heavily damp any parasitic resonance of lead or trace inductance working against the supply bypass capacitors. the opposite is true for ltc1647 hot swap circuits on a daughterboard. in most cases, on the powered side of the mosfet switch (v cc ) there is no supply bypass capacitor present. an abrupt connection, produced by plugging a board into a backplane connector, results in a fast rising edge applied to the v cc line of the ltc1647. no bulk capacitance is present to slow the rate of rise and heavily damp the parasitic resonance. instead, the fast edge shock excites a resonant circuit formed by a combi- nation of wiring harness, backplane and circuit board parasitic inductances and mosfet capacitance. in theory, the peak voltage should rise to 2x the input supply, but in practice the peak can reach 2.5x, owing to the effects of voltage dependent mosfet capacitance. the absolute maximum v cc potential for the ltc1647 is 17v; any circuit with an input of more than 6.8v should be scrutinized for ringing. a well-bypassed backplane should not escape suspicion: circuit board trace inductances of as little as 10nh can produce sufficient ringing to overvoltage v cc . check ringing with a fast storage oscilloscope (such as a lecroy 9314al dso) by attaching coax or a probe to v cc and gnd, then repeatedly inserting the circuit board into the backplane. figures 9a and 9b show typical results in a 12v application with different v cc lead lengths. the peak amplitude reaches 22v, breaking down the esd protection diode in the process. there are two methods for eliminating ringing: clipping and snubbing. a transient voltage suppressor is an effec- tive means of limiting peak voltage to a safe level. figure 10 shows the effect of adding an on semiconduc- tor, 1sma12cat3, on the waveform of figure 9. figures 11a and 11b show the effects of snubbing with different rc networks. the capacitor value is chosen as 10x to 100x the mosfet c oss under bias and r is selected for best damping1 w to 50 w depending on the value of parasitic inductance. supply glitching ltc1647 hot swap circuits on the backplane are generally used to provide power-up/down sequence at insertion/ removal as well as overload/short-circuit protection. if a short-circuit occurs at supply ramp-up, the circuit breaker trips. the partially enhanced mosfet, q1, is easily dis- connected without any supply glitch. applicatio s i for atio wu u u
ltc1647-1/ltc1647-2/ltc1647-3 13 if a dead short occurs after a supply connection is made (figure 12), the sense resistor r1 and the r ds(on) of fully enhanced q1 provide a low impedance path for nearly unlimited current flow. the ltc1647 discharges the gate pin in a few microseconds, but during this discharge time current on the order of 150 amperes flows from the v cc power supply. this current spike glitches the power sup- ply, causing v cc to dip (figure 12a and 12b). on recovery from overload, some supplies may over- shoot. other devices attached to this supply may reset or malfunction and the overshoot may also damage some components. an inductor (1 m h to 10 m h) in series with q1s source limits the short-circuit di/dt, thereby limiting the peak current and the supply glitch (figure 12c and 12d). additional power supply bypass capacitance also reduces the magnitude of the v cc glitch. v id power controller the two hot swap channels of the ltc1647 are ideally suited for v id power control in portable computers. figure 13 shows an application using the ltc1647-2 on the system side of the device bay interface (1394 phy and/ or usb). the controller detects the presence of a periph- eral in each device bay and controls the ltc1647-2. the timing waveform illustrates the following sequence of events: t1, rising out of undervoltage lockout with gate 1 ramping up; t2, load current fault at r1; t3, circuit breaker resets with r5/c3 delay; t4/t5, controller gates off/on device supply with rc delay; t6, device enters undervolt- age lockout. if c6 is not connected in figure 13, fault 2 and on2 will have similar waveforms. t7 initiates an on sequence; t8, a load fault is detected at r7 with fault 2 pulling low. if the controller wants to stretch the interval between retries, it can pull on2 low at t9 ( t9 C t8 < 0.4?t reset ). at t10/t11, the controller initiates a new power-up/down sequence. applicatio s i for atio wu u u
ltc1647-1/ltc1647-2/ltc1647-3 14 figure 8. staggered pins connection applicatio s i for atio wu u u sense 15 13 fault v cc v out fault on 3 on 2 gnd 8 gate ltc1647-3 c1 backplane connector staggered pcb edge connector r2 r1 q1 c load + v cc 1 r3 r5 r4 q2 (a) hot swap controller on motherboard sense 15 13 fault v cc v out fault 3 on 2 gnd 8 gate ltc1647-3 c1 1647-1/2/3 f08 r2 r1 q1 c load + v cc 1 r3 backplane connector staggered pcb edge connector (b) hot swap controller on daughterboard r4
ltc1647-1/ltc1647-2/ltc1647-3 15 figure 9. ring experiment v out c1 10nf 1647-1/2/3 f09 r2 10 r1 0.01 12v q1 irf7413 c load + + ltc1647 power leads scope probe 8' 1 s/div 1647-1/2/3 f09a 4v/div 0v 24v 1 s/div 4v/div 1647-1/2/3 f09b 0v 24v (a) undamped v cc waveform (48" leads) (b) undamped v cc waveform (8" leads) applicatio s i for atio wu u u
ltc1647-1/ltc1647-2/ltc1647-3 16 figure 10. transient suppressor clamp figure 11. snubber fixes applicatio s i for atio wu u u v out c1 10nf 1647-1/2/3 f10 r2 10 d1* on semiconductor * 1sma12cat3 r1 0.01 12v q1 irf7413 c load + + ltc1647 power leads backplane connector pcb edge connector 1 s/div 1647-1/2/3 f10a 2v/div 0v 12v v out c1 10nf 1647-1/2/3 f11 r2 10 r1 0.01 12v q1 irf7413 c load + + ltc1647 power leads backplane connector pcb edge connector r3 10 c1 0.1 f 1 s/div 1647-1/2/3 f11a 2v/div 0v 12v 1 s/div 1647-1/2/3 f11b 2v/div 0v 12v v cc waveform clamped by a transient suppressor (a) v cc waveform damped by a snubber (15 w , 6.8nf) (b) v cc waveform damped by a snubber (10 w , 0.1 m f)
ltc1647-1/ltc1647-2/ltc1647-3 17 applicatio s i for atio wu u u figure 12. supply glitch c1 10nf 1647-1/2/3 f12 r2 10 r1 0.01 12v q1 irf7413 l1 2 h + ltc1647 supply glitch backplane connector board with possible short-circuit fault c2 100 f + 1 s/div 25a/div 1647-1/2/3 f12a 1 s/div 4v/div 1647-1/2/3 f12b v cc gate 1 s/div 5a/div 1647-1/2/3 f12c 1 s/div 4v/div 1647-1/2/3 f12d gate v cc (a) v cc short-circuit supply current glitch without any limiting (b) v cc supply glitch without any limiting (c) v cc short-circuit supply current glitch with 2 m h series inductor (d) v cc supply glitch with 2 m h series inductor
ltc1647-1/ltc1647-2/ltc1647-3 18 applicatio s i for atio wu u u figure 13. v id power controller with fault status and retry sequence v cc sense 1 1 86 on1/fault 1 c4 10nf 2 on2/fault 2 3.3v v id supply 3 gnd 4 gate 1 sense 2 75 gate 2 ltc1647-2 connector #1 1394 phy and/or usb port device #1 c1 10nf r2 10 r1 0.1 q1 1/2 mmdf3n02hd r7 0.1 q2 1/2 mmdf3n02hd r5 10 r3** r4** c load * *c load is user-selected based on the device requirements ** r3, r4, r7 and r8 are optional discharge resistors when devices are powered-off q1, q2: on semiconductor r8 10 + connector #2 1394 phy and/or usb port device #2 r9** r10** c load * + c3 0.1 f r6 10 c6 0.1 f on1 fault 1 on2 fault 2 device bay controller with 1394 phy and/or usb v id v on1 v r1 v gate1 v fault1 v on2 v r7 v gate2 v fault2 v lko v ih v ih v lko ? v lkh v il fault 1 waveform shown with c3 fault 2 waveform shown without c6 t4 t5 t1 t7 t8 1647-1/2/3 f13 t2 t9 t10 t11 t3 t6
ltc1647-1/ltc1647-2/ltc1647-3 19 s8 package 8-lead plastic small outline (narrow 0.150) (ltc dwg # 05-08-1610) gn package 16-lead plastic ssop (narrow 0.150) (ltc dwg # 05-08-1641) package descriptio u dimensions in inches (millimeters) unless otherwise noted. gn16 (ssop) 1098 * dimension does not include mold flash. mold flash shall not exceed 0.006" (0.152mm) per side ** dimension does not include interlead flash. interlead flash shall not exceed 0.010" (0.254mm) per side 12 3 4 5 6 7 8 0.229 ?0.244 (5.817 ?6.198) 0.150 ?0.157** (3.810 ?3.988) 16 15 14 13 0.189 ?0.196* (4.801 ?4.978) 12 11 10 9 0.016 ?0.050 (0.406 ?1.270) 0.015 0.004 (0.38 0.10) 45 0 ?8 typ 0.007 ?0.0098 (0.178 ?0.249) 0.053 ?0.068 (1.351 ?1.727) 0.008 ?0.012 (0.203 ?0.305) 0.004 ?0.0098 (0.102 ?0.249) 0.0250 (0.635) bsc 0.009 (0.229) ref 0.016 ?0.050 (0.406 ?1.270) 0.010 ?0.020 (0.254 ?0.508) 45 0 ?8 typ 0.008 ?0.010 (0.203 ?0.254) so8 1298 0.053 ?0.069 (1.346 ?1.752) 0.014 ?0.019 (0.355 ?0.483) typ 0.004 ?0.010 (0.101 ?0.254) 0.050 (1.270) bsc 1 2 3 4 0.150 ?0.157** (3.810 ?3.988) 8 7 6 5 0.189 ?0.197* (4.801 ?5.004) 0.228 ?0.244 (5.791 ?6.197) dimension does not include mold flash. mold flash shall not exceed 0.006" (0.152mm) per side dimension does not include interlead flash. interlead flash shall not exceed 0.010" (0.254mm) per side * ** information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
ltc1647-1/ltc1647-2/ltc1647-3 20 linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 l fax: (408) 434-0507 l www.linear-tech.com ? linear technology corporation 1999 1647f lt/tp 0100 4k ? printed in usa related parts typical applicatio u part number description comments ltc1421 2-channel hot swap controller 24-pin, operates from 3v to 12v and supports C12v ltc1422 hot swap controller in so-8 system reset output with programmable delay lt1640l/lt1640h negative voltage hot swap controller in so-8 operates from C10v to C80v lt1641 high voltage hot swap controller in so-8 operates from 9v to 80v lt1642 fault protected hot swap controller operates up to 16.5v, protected to 33v ltc1643l/ltc1643h pci-bus hot swap controller 3.3v, 5v and 12v in narrow 16-pin ssop lt1645 2-channel hot swap controller operates from 1.2v to 12v, power sequencing hot swapping two supplies two separate supplies can be independently controlled by using the ltc1647-3. in some applications, sequencing between the two power supplies is a requirement. for example, it may be necessary to ramp-up one supply first before allowing the second supply to power-up, as well as requiring that this same supply ramp-down last on power- down. figure 14s circuit illustrates how to program the delays between the two pass transistors using the on1 and on2 pins (time events t1 to t4). t5 and t7 show both channels being switched on simultaneously where se- quencing is not crucial. some applications require that both channels be gated off if a fault occurs in one channel. this is accomplished in figure 14 by using a crisscross fault-to-sense arrange- ment of r3/r4 and r7/r8. t6 and t9 illustrate the circuits operation. figure 14. hot swapping two supplies sense 1 15 13 fault 2 5v supply v out1 (5a) fault gnd on2 on1 5 on2 4 fault 1 3 on1 2 gnd 8 gate 1 ltc1647-3 c1 10nf r2 10 r1 0.01 q1 irf7413 r3 100 c load + v cc1 sense 2 gate 2 v cc2 1 14 12 16 r8 100 12v supply v out2 (2.5a) c load + r5 10k r6 10k r4 4.7k r7 12k c3 10nf q2 irf7413 r9 10 r10 0.02 connector v r1 v r10 v on1 v on2 v out1 v out2 t6 t9 1647-1/2/3 f14 t3 t2 t1 t4 t5 t7 t8

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